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| V292BMC Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS * Pin/Software compatible with earlier V292BMC. * Direct interfaces to Am29030/40 processors. * 3.3V DRAM interface support. * Near SRAM performance achieved with DRAM. * Supports up to 512Mb of DRAM. * Interleaved or non-interleaved operation. * Supports symmetric and non-symmetric arrays. The V292BMC Revision D Burst DRAM Controller is an enhanced version of the previous V292BMC with improved timing and provides dedicated Power and Ground rails to support the increasingly popular 3.3V DRAM modules. Timing parameters are also improved over the older versions of the device. The V292BMC provides the DRAM access protocols, buffer signals, data multiplexer signals, and bus timing resources required to work with DRAM. By using the V2926BMC, system designers can replace tedious design work, expensive FPGAs and valuable board space with a single, high-performance, easily configured device. The processor interface of the V292BMC implements the bus protocol of the Am29030/40. The pin naming convention has been duplicated on the V292BMC; simply wire like-named pins together to create the interface. The V292BMC supports a total DRAM memory subsystem size of 512Mbytes. The array may be * Software-configured operational parameters. * Integrated Page Cache Management. * 2Kbyte burst transaction support. * On chip memory address multiplexer/drivers. * Two 24-bit timers, 8-bit bus watch timer. * Up to 40MHz operation. * Low cost 132-pin PQFP package. organized as 1 or 2 leafs of 32-bits each. Standard memory sizes of 256Kbit to 64Mbit devices are supported and 8, 16, and 32-bit accesses are allowed. The V292BMC takes advantage of Fast Page Mode or EDO DRAMs and row comparison logic to achieve static RAM performance using dynamic RAMs. Control signals required for optional external data path buffers/latches are also provided by the V292BMC. The V292BMC provides an 8-bit bus watch timer to detect and recover from accesses to unpopulated memory regions.Two 24-bit counters/timers can supply an external interrupt signal at a constant frequency relative to the system clock. The V292BMC is packaged in a low-cost 132-pin PQFP package and is available in 25, 33, or 40MHz versions. This document contains the product codes, pinouts, package mechanical information, DC characteristics, and AC characteristics for the V292BMC. Detailed functional information is contained in the User's Manual. Am29030/40 CPU V292BMC MEMORY CONTROL D R A M ROM TYPICAL APPLICATION VxxxEPC LOCAL TO PCI BRIDGE PCI SLOT or EDGE CONNECTOR PCI PERIPHERAL Copyright (c) 1998, V3 Semiconductor Corp. V292BMC Data Sheet Rev 3.2X 1 V3 Semiconductor reserves the right to change the specifications of this product without notice. V292BMC is trademark of V3 Semiconductor. All other trademarks are the property of their respective owners. V292BMC Rev.D V3 Semiconductor retains the rights to change documentation, specifications, or device functionality at any time without notice. Please verify that you have the latest copy of all documents before finalizing a design. 1.0 Product Codes Table 1: Pin Types Product Code V292BMC-33LP V292BMC-40LP Processor Am29030/35/40 Am29030/35/40 Bus Type 32-bit demultiplexed 32-bit demultiplexed Package 132-pin PQFP 132-pin PQFP Frequency 33MHz 40MHz 2.0 Pin Description and Pinout Table 2 below lists the pin types found on the V292BMC. Table 3 describes the function of each pin on the V292BMC. Table 4 lists the pins by pin number. Figure 1 shows the pinout for the 132-pin PQFP package and Figure 2 shows the mechanical dimensions of the package. Table 2: Pin Types Pin Type I/O12 I O12 Description TTL I/O pin with 12 mA output drive TTL input only pin TTL Output pin with 12 mA output drive TTL Output pin with 12 mA output drive that can be configured for either 5 volt or 3.3 volt signaling, These outputs can be configured for 3.3V operation by connecting the Vcc3 power pins to a 3.3V power plane (Vcc should always be connected to a 5V supply). Vcc3 can also be connected to the 5V plane if 5V signaling is desired. O12-3 2 V292BMC Rev D Data Sheet Rev 3.2 Copyright (c) 1998, V3 Semiconductor Inc. V292BMC Rev.D Table 3: Signal Descriptions Memory Interface Signals Signal AA[11:0] AB[11:0] Type O12-3 Ra X Description Leaf A and B row and column address, multiplexed on the same pins. When non-interleaved operation is selected, only address bus AA should be used. Row Address Strobe. These strobes indicate the presence of a valid row address on busses AA(B)[11:0]. These signals are to be connected one to each 32-bit leaf of memory. Column Address Strobe. These strobes latch a column address from AA(B)[11:0]. They are assigned one to each byte in a leaf. Memory Write Enable. These are the DRAM write strobes. One is supplied for each leaf to minimize signal loading. Refresh in progress. This output is multi-function signal. The signal name, as it appears on the logic symbol, is the default signal names. This signal gives notice that a refresh cycle is to be executed. The timing leads RAS only refresh by one cycle. The output may also function as AUX timer interrupt. RASA[3:0] RASB[3:0] CASA[3:0] CASB[3:0] MWEA MWEB O12-3 H O12-3 O12-3 H H RFS/AUXT O12 H Configuration Signal MOD4 Type I R Description Selects Modulo 4 (word) bursting for multiplexed address AA(B). Buffer Controls Signals Signal Type R Description Data Transmit A and B. These outputs are multi-function signals. The signal names, as they appear on the logic symbol, are the default signal names (Mode 0). The purpose of these outputs is to control buffer output enables during data read transactions and, in effect, control the multiplexing of data from each memory leaf onto the Am29030/40 data bus. These outputs are mode independent, however, the timing of the signals change for different operational modes. They control transparent latches that hold data transmitted during a write transaction. In modes 0 and 1, the latch controls follow the timing of CAS for each leaf, while in modes 2 and 3 the timing of LEA and LEB is shortened to 1/2 clock. Local Bus Interface TXA TXB O12 H LEA LEB O12 L Copyright (c) 1998, V3 Semiconductor Corp. V292BMC Rev D Data Sheet Rev 3.2 3 V292BMC Rev.D Table 3: Signal Descriptions (cont'd) Signal A[31:2] Type I R Local address bus. Address Latch Enable: controls a set of transparent latches on the address bus. When asserted high, the address input flows through the latch. When ALE is low, the internal address holds the previous value. With an Am29030/40 processor ALE is not typically used and has an internal pull-up resistor that will keep it high when not connected (to provide backward pin compatibility with earlier versions). Data/Code. Local bus byte write enables. Read/write. Asserted low to indicate the beginning of a bus cycle. Z Local bus data ready. Processor ready Indicates supervisor mode. Required for access to configuration registers. Burst request. H H Bus Time-out error. Local interrupt request. This signal is asserted when the 24-bit counter reaches terminal count, and interrupt out is enabled. May be programmed for pulse or level operation. Local bus reset signal. Local bus clock. These inputs select the address offset of the configuration registers. Power and Ground Signals Signal Vcc Vcc3 GND Type R Description POWER leads intended for external connection to a 5V Vcc plane POWER for DRAM control outputs. Can be connected to 3.3V or 5V. GROUND leads intended for external connection to a GND plane. Description ALE I I/D BWE[3:0] R/W REQ RDY PRDY SUP/US BURST ERR INT RESET MEMCLK ID[2:0] I I I I O12 I I I O12 O12 I I I a. R indicates state during reset. 4 V292BMC Rev D Data Sheet Rev 3.2 Copyright (c) 1998, V3 Semiconductor Inc. V292BMC Rev.D Table 4: Pin Assignments PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Signal A14 A15 A16 Vcc A17 A19 A20 A18 A21 A24 A22 A23 A26 A25 A27 ALE A31 A28 A29 A30 I/D SUP/US MEMCLK INT ERR PIN # 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Signal REQ BWE2 BWE3 GND RDY ID0 ID1 ID2 RFS/AUXT LEA LEB TXA TXB Vcc GND AA0 AA1 AA2 AA3 Vcc3 GND AA4 AA5 PIN # 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Signal AA10 AA11 Vcc3 GND CASA0 CASA1 CASA2 CASA3 Vcc3 GND RASA0 RASA1 RASA2 RASA3 Vcc3 MWEA GND AB0 AB1 AB2 AB3 Vcc3 GND AB4 PIN # 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Signal AB9 AB10 AB11 Vcc3 GND CASB0 CASB1 CASB2 CASB3 Vcc3 GND RASB0 RASB1 RASB2 RASB3 Vcc MOD4 MWEB GND RESET A2 A3 A4 A5 A6 A7 Copyright (c) 1998, V3 Semiconductor Corp. V292BMC Rev D Data Sheet Rev 3.2 5 V292BMC Rev.D Table 4: Pin Assignments (cont'd) PIN # 28 29 30 31 32 33 Signal R/W BWE0 PRDY BURST BWE1 GND PIN # 61 62 63 64 65 66 Signal AA6 AA7 Vcc3 GND AA8 AA9 PIN # 94 95 96 97 98 99 Signal AB5 AB6 AB7 Vcc3 GND AB8 PIN # 127 128 129 130 131 132 Signal A8 A9 A10 A11 A12 A13 Figure 1: Pinout for 132-pin PQFP (top view) 6 V292BMC Rev D Data Sheet Rev 3.2 Copyright (c) 1998, V3 Semiconductor Inc. V292BMC Rev.D Figure 2: 132-pin PQFP mechanical details Copyright (c) 1998, V3 Semiconductor Corp. V292BMC Rev D Data Sheet Rev 3.2 7 V292BMC Rev.D 3.0 DC Specifications Table 5: Absolute Maximum Ratings Symbol VCC VIN IIN TSTG Supply voltage DC input voltage DC input current Storage temperature Parameter Rating -0.3 to +7 -0.3 to VCC+0.3 50 -65 to +150 Units V V mA C Table 6: Guaranteed Operating Conditions Symbol VCC,VCC3 VCC3 TA Supply voltage Supply voltage for 3.3 Volt DRAM interface operation1. Vcc is still as above Ambient temperature range Parameter Rating 4.75 to 5.25 3.0 to 3.6 0 to 70 Units V V C 1. For 3.3 Volt DRAM intreface operation.(See also note 8 table 11) Table 7: DC Operating Specifications Vcc=5 Volt and Vcc3=5 Volt Symbol VIL VIH IIL IIH VOL VOH Description Low level input voltage High level input voltage Low level input current High level input current Low level output voltage High level output voltage Conditions Vcc = 4.75V Vcc = 5.25V VIN = GND, VCC = 5.25V VIN = VCC = 5.25V VIN = VIL or VIH IOL = -12 mA VIN = VIL or VIH IOL = -12 mA VCC -1.0 2.0 -10 10 0.4 Min Max 0.8 Units V V A A V V 8 V292BMC Rev D Data Sheet Rev 3.2 Copyright (c) 1998, V3 Semiconductor Inc. V292BMC Rev.D Table 7: DC Operating Specifications Vcc=5 Volt and Vcc3=5 Volt Symbol IOZL IOZH ICC (max) CIO Description Low level float input leakage High level float input leakage Maximum supply current Input and output capacitance Conditions VIN = VIL or VIH VO = -GND VIN = VIL or VIH VO = -5.25V Continuous simple access Continuous burst access Min -20 20 100 30 20 Max Units A A mA pF Table 8: DC Operating Specifications Vcc3=3.3 Volt and Vcc=5 Volt Symbol VOL VOH IOZL IOZH ICC (max) Description Low level output voltage High level output voltage Low level float input leakage High level float input leakage Maximum supply current Conditions VIN = Vcc3 IOL = 12 mA VIN = Vcc3 IOL = -12 mA VIN = Vcc3 VO = GND VIN = Vcc3 VO =4.465 V Continuous simple access Continuous burst access 2.4 -10 10 140 40 Min Max 0.4 Units V V A A mA 4.0 AC Specifications Table 9: AC Test Conditions Symbol VCC, VCC3 VCC3 VIN COUT Supply voltage Supply voltage for 3.3 Volt DRAM interface operation1 (Vcc is still as above) Input low and high voltages Capacitive load on output and I/O pins Parameter Limits 4.75 to 5.25 4.75 to 5.25 0.4 and 4.25 50 Units V V V pF 1. For 3.3 Volt DRAM interface operation.(See also note 8 table 11) Copyright (c) 1998, V3 Semiconductor Corp. V292BMC Rev D Data Sheet Rev 3.2 9 V292BMC Rev.D Table 10: Capacitive Derating for Output and I/O Pins Output Drive Limit 12 mA 12 mA Supply voltage Vcc=5 Volt, Vcc3=3.3 Volt Vcc=5 Volt, Vcc3=5 Volt Derating 0.06 ns/pF for loads > 50 pF 0.04 ns/pF for loads > 50 pF Table 11: Timing Parameters for V292BMC Vcc = 5 Volts +/- 5% and Vcc3 = 5 or 3.38 Volts +/- 5% 33 MHz Symbol tC tCH tCL tSU tH tH tRZH tRHL tRLH tRHZ tEHL tELH tIHL tILH tARA1 tARA2 tRAH tCAV tCAH tBCAV tRHL tRLH tRAS tRSH tRP tCHL Description MEMCLK period MEMCLK high time MEMCLK low time Synchronous input setup Synchronous input hold Synchronous input hold (RESET#) RDY 3-state to valid delay RDY synchronous assertion delay RDY synchronous de-assertion delay RDY valid to 3-state delay ERR synchronous assertion delay ERR synchronous de-assertion delay INT synchronous assertion delay INT synchronous de-assertion delay Address Input to Row Address output delay (Interleaved) Address Input to Row Address output delay (Non-interleaved) Row address hold from RAS assertion Column address valid from RAS assertion Column address hold from CAS assertion Column address valid delay from previous CAS assertion (Burst) MEMCLK to RAS asserted delay MEMCLK to RAS de-asserted delay RAS pulse width RAS hold from last CAS assertion RAS precharge time MEMCLK to CAS asserted delay 3 4 5 1 3 3 3tC-1 tN tP-2 3 13 2 2 1 1 3 3 3 3 3 3 3 3 3 4 tM tM+1 tC tC+3 13 13 3 3 3tC-1 tN tP-2 3 12 Note Min 30 12 12 9 1 3 13 13 13 10 13 12 13 12 14 18 tM+2 tM+4 3 3 3 3 3 3 3 3 3 4 tM tM+1 tC tC+3 11 11 Max 40 MHz Min 25 11 11 8 0.5 3 10 11 11 7 11 10 11 10 12 15 tM+2 tM+4 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 V292BMC Rev D Data Sheet Rev 3.2 Copyright (c) 1998, V3 Semiconductor Inc. V292BMC Rev.D Table 11: Timing Parameters for V292BMC Vcc = 5 Volts +/- 5% (cont'd)and Vcc3 = 5 or 3.38 Volts +/- 5% tCLH tCAS tCPN tRCD tWESU tWEH tLED tTXHL1 tTXHL2 tTXLH tRFHL tRFLH tASU MEMCLK to CAS de-asserted delay CAS pulse width CAS precharge time RAS to CAS delay time Write Enable setup to RAS assertion Write Enable hold from RAS de-assertion MEMCLK to Latch Enable output delay MEMCLK to Buffer Control fall delay MEMCLK to Buffer Control fall delay (Mode 2 and 3 at TXA pin only) MEMCLK to Buffer Control rise delay REFRESH synchronous assertion delay REFRESH synchronous de-assertion delay Address setup to ALE Falling 6 7 4 4 tN-1 0.5tC 1.5tC-2 12 3 tN-1 0.5tC 11 ns ns ns ns ns 1.5tC 1.5tC-2 1.5tC 9 3 12 13 15 12 13 13 1 3 3 4 3 3 3 5 3 10 11 13 10 11 11 10 1 3 3 4 3 3 3 6 ns ns ns ns ns ns ns ns tAH Address hold from ALE Falling 5 4 ns NOTES: 1. Specified from MEMCLK falling edge. 2. tM = tC when T_MUX = 1; tM = 0.5 * tC when T_MUX = 0. 3. Maximum RAS pulse width depends on the number of burst access. 4. tN = 1.5 * tC when T_RAS = 0; tN = 2.5 * tC when T_RAS = 1. 5. tP = 2 * tC when T_RAS = 0; tP = 2 * tC when T_RAS = 1 and T_RP = 1; tP = 3 * tC when T_RAS = 1 and T_RP = 0. 6. Rising delay is measured from MEMCLK falling edge, falling delay is measured from MEMCLK rising edge. 7. Except for Mode 2 and 3 at TXA pin. 8. In order to have 3.3 Volt DRAM interface Vcc3 pins must be connected to 3.3 Volt. Vcc3 pins are: PIN # 91, 97, 103, 57, 63, 69, 75, 81. The power supply pins that must always be connected to 5 Volt are Vcc. Vcc pins are: PIN # 4, 47, 115. Figure 3: Clock and Synchronous Signals Copyright (c) 1998, V3 Semiconductor Corp. V292BMC Rev D Data Sheet Rev 3.2 11 V292BMC Rev.D Figure 4: ALE Timing Figure 5: Basic Access Timing 12 V292BMC Rev D Data Sheet Rev 3.2 Copyright (c) 1998, V3 Semiconductor Inc. V292BMC Rev.D Figure 6: Burst Access Timing Copyright (c) 1998, V3 Semiconductor Corp. V292BMC Rev D Data Sheet Rev 3.2 13 V292BMC Rev.D 5.0 Revision History Table 12: Revision History Revision Number 3.2 3.1 3.0 2.0 1.0 Date 7/98 10/96 05/96 7/92 7/92 Comments and Changes V292BMC Rev D timing parameters with 3.3V DRAM support. Data Book revision. Updated timings to final D-step values. Simplified data sheet format. Updated timings to final A-step values. First pre-silicon revision of preliminary data sheet. DC and AC specs TBD. Sent only to a limited number of customers 14 V292BMC Rev D Data Sheet Rev 3.2 Copyright (c) 1998, V3 Semiconductor Inc. |
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